Tuneable delay line

ABSTRACT

An electrical conductor delay line with an MIS structure.

United States Patent 1 1 Harth et al.

[ 51 Oct.7, 1975 [541 TUNEABLE DELAY LINE [75] Inventors: Wolfgang Harth; Jorg Muller, both of Braunschweig, Germany [73] Assignee: Licentia Patent-Verwaltungs-G.m.b.I-l., Frankfurt am Main, Germany [22] Filed: July 6, 1973 [21] Appl. No.: 377,019

[30] Foreign Application Priority Data OTHER PUBLICATIONS Hasegawa et al., Measurements on High-Frequency Transmission Characteristics of Metallization Patterns in Monolithic ICs, Electronics and Communications in Japan, Vol. 548, No. 3, 1971, pp. 52-60.

Frankel, D. R., Some Effects of Material Parameters on the Design of Surface Space-Charge Varactors, Solid State Electronics, Vol. 2, No. 1, 1961, pp. 71-76.

Ho, I. T., Analysis of Transmission Lines on Integrated-Circuit Chips, IEEE Jr. of Solid State Circuits, SC-2, 1967, pp. 201-208.

I-lasegawa et al., Properties of Microstrip Line on Si- SiO Systems, MTT-19, 1971, pp. 869-881. I-lasegawa, et al., Slow Wave Propagation Along the Transmission Line on Si-SiO System, Annu. Rep. Eng. Res. Inst. Fac. Eng. Univ., Tokyo (Japan), Vol. 29, (9-1970), pp. 87-92.

Yamashita, et al., Variational Method for the Analysis of Microstrip Lines, M'I'I, 16, 1968, pp. 251-256. Brennan et al., Delay Line for Use with Integrated Circuits," IBM Tech. Disclosure Bu11., Vol. 9, No. 1 1, 4-1967, pp. 1635-1636.

Primary Examiner-Alfred E. Smith Assistant Examiner-Wm. H. Punter Attorney, Agent, or Firm-Spencer & Kaye [5 7] ABSTRACT An electrical conductor delay line with an M15 structure.

13 Claims, 3 Drawing Figures out US. Patent Oct. 7,1975 3,911,382

'Z'(Ub) in) ouf (we) TUNEABLE DELAY LINE BACKGROUND OF THE INVENTION This invention relates to electrical conductors.

SUMMARY OF THE INVENTION It is an object of this invention to provide a new structure for an electrical conductor.

According to the invention, there is provided an electrical conductor, comprising a conductor with a metal insulator semiconductor structure.

BRIEF DESCRIPTION OF THE DRAWINGS.

The invention will now be described in greater detail, by way of example, with reference to the drawings, in which:

FIG. 1 is a perspective view of one form of electrical conductor according to the invention;

FIG. 2 is a diagram showing the use of an electrical conductor according to the invention as a delay line, and;

FIG. 3 is an equivalent circuit diagram of the circuit according to FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Basically it is proposed, in accordance with the invention, that the electrical conductor has an MIS structure. The electrical conductor according to the invention is suitable for example as an electronically tunable delay line.

What is understood as an MIS structure is a structure which comprises the material sequence metal, insulator, semiconductor. The metal and the semiconductor in this case are separated from each other by an insulator or an insulating layer. The metal is preferably applied as a conductive path on the insulating layer. The width of the conductive path is, according to one form of embodiment of the invention, chosen to be less than the width of the semiconductor or the insulating layer thereon. An electrical contact is applied to the semiconductor of the electrical conductor. This is effected, for example, on the side of the semiconductor opposite the insulator.

If an electrical conductor in accordance with the invention is constructed as an MIS structure, a strip line is obtained, the capacitance per unit length of which depends both on the alternating voltage applied to the conductor and on the direct voltage applied. With suitable dimensioning there occurs on such an electrical line a slow wave mode with particularly low phase speed and damping.

The Specific resistance of the semiconductor and the thickness of the insulator are of particular importance for the dimensioning of the electrical conductor according to the invention. If the specific resistance of the semiconductor is chosen to be between 5.10 and 5.10 Ohmcm and the thickness of the insulator is chosen to be between 500 and 2000 A, a slow wave mode in a frequency region between 100 MHz and a few GHZ is obtained.

The insulator comprises for example SiO Si N A1 or a double layer of SiO jSi N., or SiO /Al O For example, silicon is chosen as the material for the semiconductor.

A space charge region arises in the semiconductor, and thus a space charge capacitance, by applying a suitable voltage to the MIS conductor. When changing the voltage applied, the space charge capacitance also changes and in so doing also the characteristic impedance of the MIS conductor, whereby also the phase speed of the slow wave mode is changed. The transit time of the slow wave on the MIS conductor therefore depends on the direct voltage applied. Such an MIS conductor is therefore suitable as an electronically tunable delay line.

Referring now to the drawings, an electrical conductor with MIS structure according to the invention is shown in FIG. 1. According to FIG. 1, the electrical conductor comprises a metallic conductive path 1, an insulator 2, a semiconductor 3 and an electrical contact 4 on the semiconductor. As is obvious from FIG. 1, the width of the conductor path 1 is chosen to be smaller than the width of the semiconductor 3 or the insulating layer 2 located on the semiconductor.

The conductive path 1 has, for example a width of 10 to 50 um. The insulating layer 2 is for example 500 to 2,000 A thick. The thickness of the semiconductor amounts to approximately to 200 um. The semiconductor material is chosen, for example, such that it has a specific resistance of from 5.10 to 5.10 Ohmcm.

For use as a delay line of length 1, according to FIG. 2 an input signal V,-,, is coupled in at the input of the conductor L and is uncoupled at the end of the conductor L as a delayed signal V,,,,,. The delay or transit time '1- of the signal thus depends both on the voltage V applied and on the conductor length l. The direct voltage necessary to change the delay time is fed, in accordance with FIG. 2, through a high-value resistance R,,, which has for example a resistance of l MOhm in the exemplary embodiment. As FIG. 2 shows further, the electrical conductor is electrically separated from the outer circuit by the series capacitances C and C The resistances R and R serve for the coupling in and the uncoupling of the signal respectively. FIG. 3 shows the equivalent circuit diagram of the arrangement in accordance with FIG. 2.

It will be understood that the above description of the present invention is susceptible to various modification changes and adaptations.

What is claimed is:

1. A variable delay line consisting of in combination:

a semiconductor body;

a layer of insulating material on one surface of said semiconductor body;

a stripwise metal conductor on the surface of said insulating layer, said conductor having a width which is smaller than the width of said insulating layer and of said semiconductor body;

an electrical contact applied to the surface of said semiconductor body opposite to said one surface; and

means for applying a variable direct voltage to said conductor, whereby the delay time of the electrical wave on said conductor resulting from the application of an electrical signal to one end thereof is determined by the value of the applied direct voltage.

2. A delay line as defined in claim 1, wherein said semiconductor has a specific resistance of between 5.10 and 5.10" Ohmcm.

3. A delay line as defined in claim 2, wherein said insulator has a thickness of between 500 and 2000 A.

4. A delay line as defined in claim 3, wherein said conductive path has a width between and 50 um.

5. Use of the delay line according to claim 4 for a slow wave mode in a frequency range between 100 MHz and a few GHZ.

6. A delay line as defined in claim 1, wherein said semiconductor body is formed of silicon.

7. An electrical conductor as defined in claim 6, wherein said insulator comprises SiO Si N or A1 0 8. A delay line as defined in claim 7, wherein said insulator comprises a double layer insulator.

9. A delay line as defined in claim 8, wherein one layer of said double layer insulator comprises SiO and the other layer of said double layer insulator comprises Si N 10. A delay line as defined in claim 8, wherein one layer of said double layer insulator comprises SiO and the other of said double layer insulator comprises Al 11. A delay line as defined in claim 1 wherein said means for applying a direct voltage includes a direct voltage source, a resistance, and means for feeding the direct voltage through said resistance to said metal conductor.

12. A delay line as defined in claim 11, wherein said resistance comprises a resistance of high value.

13. A delay line as defined in claim 11 further comprising capacitances for separating said delay line from the rest of the circuit and positioned at the input and output sides of said delay line. 

1. A variable delay line consisting of in combination: a semiconductor body; a layer of insulating material on one surface of said semiconductor body; a stripwise metal conductor on the surface of said insulating layer, said conductor having a width which is smaller than the width of said insulating layer and of said semiconductor body; an electrical contact applied to the surface of said semiconductor body opposite to said one sUrface; and means for applying a variable direct voltage to said conductor, whereby the delay time of the electrical wave on said conductor resulting from the application of an electrical signal to one end thereof is determined by the value of the applied direct voltage.
 2. A delay line as defined in claim 1, wherein said semiconductor has a specific resistance of between 5.10 2 and 5.10 1 Ohmcm.
 3. A delay line as defined in claim 2, wherein said insulator has a thickness of between 500 and 2000 A.
 4. A delay line as defined in claim 3, wherein said conductive path has a width between 10 and 50 um.
 5. Use of the delay line according to claim 4 for a slow wave mode in a frequency range between 100 MHz and a few GHz.
 6. A delay line as defined in claim 1, wherein said semiconductor body is formed of silicon.
 7. An electrical conductor as defined in claim 6, wherein said insulator comprises SiO2, Si3N4 or Al2O3.
 8. A delay line as defined in claim 7, wherein said insulator comprises a double layer insulator.
 9. A delay line as defined in claim 8, wherein one layer of said double layer insulator comprises SiO2 and the other layer of said double layer insulator comprises Si3N4.
 10. A delay line as defined in claim 8, wherein one layer of said double layer insulator comprises SiO2 and the other of said double layer insulator comprises Al2O3.
 11. A delay line as defined in claim 1 wherein said means for applying a direct voltage includes a direct voltage source, a resistance, and means for feeding the direct voltage through said resistance to said metal conductor.
 12. A delay line as defined in claim 11, wherein said resistance comprises a resistance of high value.
 13. A delay line as defined in claim 11 further comprising capacitances for separating said delay line from the rest of the circuit and positioned at the input and output sides of said delay line. 